1. Field of the Invention
The present invention relates to a reverse current preventing circuit and, more particularly, to a reverse current preventing circuit, which is applied in a synchronous switching voltage converter, with an automatic correction of reference so as to accurately prevent occurrence of current reversal.
2. Description of the Related Art
FIG. 1(a) is a circuit diagram showing a conventional synchronous switching voltage converter 10. The synchronous switching voltage converter 10 converts an input voltage source Vin into a regulated output voltage Vout for being supplied to a load Ld. A high-side switch SH is coupled between the input voltage source Vin and a switch node SN, while a low-side switch SL is coupled between the switch node SN and a ground potential. In the example shown in FIG. 1(a), the high-side switch SH is implemented by a PMOS transistor while the low-side switch SL is implemented by an NMOS transistor. An inductor L is coupled between the switch node SN and an output terminal O. A control circuit 11 applies a switch control signal CS to a driving circuit 12 for generating a high-side driving signal PH and a low-side driving signal PL. The high-side driving signal PH turns ON/OFF the high-side switch SH, while the low-side driving signal PL turns ON/OFF the low-side switch SL. In response to the feedback of the output voltage Vout, the control circuit 11 adjusts the duty cycle of the switch control signal CS so as to regulate the output voltage Vout. Furthermore, an output capacitor CO is coupled to the output terminal O so as to filter ripples of the output voltage Vout.
FIG. 1(b) is a waveform timing chart showing an operation of a conventional synchronous switching voltage converter 10. Through a high-side driving circuit SH and a low-side driving circuit SL, respectively, the switch control signal CS is inverted into the high-side driving signal PH and the low-side driving signal PL. During a phase from time T1 to T2, the high-side driving signal PH and the low-side driving signal PL are both at the LOW level, so the high-side switch SH is turned ON and the low-side switch SL is turned OFF such that the direction of the inductor current IL is from the switch node SN to the output terminal O (such direction is defined as the positive direction hereinafter) and the absolute value of the inductor current IL gradually increases. During a phase from time T2 to T4, the high-side driving signal PH and the low-side driving signal PL are both at the HIGH level, so the high-side switch SH is turned OFF and the low-side switch SL is turned ON such that the absolute value of the inductor current IL gradually decreases. It should be noted that at time T3 the absolute value of the inductor current IL decreases to zero, so from time T3 to T4 the direction of the inductor current IL is reversed to become from the output terminal O to the switch node SN (such direction is defined as the negative direction hereinafter). During a phase from time T4 to T6, the high-side driving signal PH and the low-side driving signal PL are both at the LOW level, so the high-side switch SH is turned ON and the low-side switch SL is turned OFF. Since at this moment the direction of the inductor current IL is negative, the absolute value of the inductor current IL gradually decreases. From time T5 on, the direction of the inductor current IL becomes positive again and the absolute value of the inductor current IL gradually increases.
In FIG. 1(b), the hatched regions indicate the phenomenon of the current reversal. When the inductor current IL is flowing along the direction from the output terminal O to the switch node SN, energy is reversely supplied from the load Ld to the synchronous switching voltage converter 10. Since the current reversal causes the efficiency of the synchronous switching voltage converter 10 to be reduced, it is necessary to prevent the occurrence of the current reversal.
FIG. 2(a) is a circuit showing a first example of a conventional reverse current preventing circuit 23. The reverse current preventing circuit 23 has a current comparing circuit 24, a fixed reference current source Ireg, and an AND logical gate 25. The current comparing circuit 24 has a non-inverting input terminal for receiving the inductor current IL, and an inverting input terminal for receiving a fixed reference current source Iref. The AND logical gate 25 has a first input terminal for receiving the switch control signal CS, and a second input terminal for receiving a preventing signal RI output from the current comparing circuit 24. The output terminal of the AND logical gate 25 is coupled to the low-side driving circuit 12L so as to determine the low-side driving signal PL.
FIG. 2(b) is a waveform timing chart showing an operation of the conventional reverse current preventing circuit 23. Hereinafter is assumed that the fixed reference current Iref is set as zero. During a phase from time T1 to T2, the switch control signal CS is at the HIGH level and the preventing signal RI is at the HIGH level, such that the high-side and low-side driving signals PH and PL are both at the LOW level. Therefore, the high-side switch SH is turned ON and the low-side switch SL is turned OFF, such that the direction of the inductor current IL is positive and the absolute value of the inductor current IL gradually increases. At time T2, the switch control signal CS changes to the LOW level, such that the high-side and low-side driving signals PH and PL are both at the HIGH level. Therefore, the high-side switch SH is turned OFF and the low-side switch SL is turned ON, such that the absolute value of the inductor current IL gradually decreases. At time T3, the preventing signal RI changes to the LOW level since the absolute value of the inductor current IL decreases to zero, thereby causing the low-side driving signal PL to become the LOW level. Therefore, the low-side switch SL is turned OFF for preventing the reversal of the inductor current IL.
However, there is actually a delay between the very moment when the absolute value of the inductor current IL decreases to zero and the very moment when the preventing signal RI is applied to the low-side switch SL since the operating speed of the current comparing circuit 24 is finite. In other words, the reversal of the inductor current IL will inevitably occur during such delay. The hatched regions shown in FIG. 2(b) indicate the incomplete prevention from the reversal of the inductor current IL due to the existence of the delay. Moreover, the operating speed of the current comparing circuit 24 changes along with the integrated circuit manufacturing process and the operating temperature. As a result, the delay caused by the current comparing circuit 24 is not a constant and therefore it is impossible to compensate the delay by using a fixed offset current.
FIG. 3(a) is a circuit showing a second example of a conventional reverse current preventing circuit 33. The reverse current preventing circuit 33 has a voltage comparing circuit 34, a fixed reference voltage source Vref, and an AND logical gate 35. The voltage comparing circuit 34 has a non-inverting input terminal for receiving a voltage VSN at the switch node SN, and an inverting input terminal for receiving a fixed reference voltage source Vref. The AND logical gate 35 has a first input terminal for receiving the switch control signal CS, and a second input terminal for receiving a preventing signal RV output from the voltage comparing circuit 34. The output terminal of the AND logical gate 35 is coupled to the low-side driving circuit 12L so as to determine the low-side driving signal PL.
FIG. 3(b) is a waveform timing chart showing an operation of the conventional reverse current preventing circuit 33. Hereinafter is assumed that the fixed reference voltage Vref is set as zero. During a phase from time T1 to T2, the switch control signal CS is at the HIGH level and the preventing signal RV is at the HIGH level, such that the high-side and low-side driving signals PH and PL are both at the LOW level. Therefore, the high-side switch SH is turned ON and the low-side switch SL is turned OFF, such that the voltage VSN at the switch node SN is pulled up to approach the input voltage source Vin. At time T2, the switch control signal CS changes to the LOW level, such that the high-side and low-side driving signals PH and PL are both at the HIGH level. Therefore, the high-side switch SH is turned OFF and the low-side switch SL is turned ON, such that the inductor current IL flows from the ground potential through the low-side switch SL to the inductor L and the output terminal O, thereby causing the voltage VSN at the switch node SN to drop rapidly and even become negative in polarity. Afterwards, the voltage VSN at the switch node SN gradually approaches the ground potential because the absolute value of the inductor current IL gradually decreases. At time T3, the preventing signal RV changes to the HIGH level since the voltage VSN at the switch node SN reaches zero and become positive in polarity, thereby causing the low-side driving signal PL to become the LOW level. Therefore, the low-side switch SL is turned OFF for preventing the reversal of the inductor current IL.
However, there is actually a delay between the very moment when the voltage VSN at the switch node SN reaches zero and the very moment when the preventing signal RV is applied to the low-side switch SL since the operating speed of the voltage comparing circuit 34 is finite. In other words, the reversal of the inductor current IL will inevitably occur during such delay. The hatched regions shown in FIG. 3(b) indicate the incomplete prevention from the reversal of the inductor current IL due to the existence of the delay. Moreover, the operating speed of the voltage comparing circuit 34 changes along with the integrated circuit manufacturing process and the operating temperature. As a result, the delay caused by the voltage comparing circuit 34 is not a constant and therefore it is impossible to compensate the delay by using a fixed offset voltage.